Thursday, June 13, 2002, 8:30 AM - 10:00 AM | Room: Auditorium B SESSION 36    Advances in Timing and Simulation    Chair: David J. Hathaway - IBM Corp., Essex Junction, VT Chair:    Organizers: Louis Scheffer, Narendra V Shenoy    This session addresses extensions to static timing to take into account statistical manufacturing variations, false paths and both! In addition to timing verification, the final paper focuses on inexpensive acceleration of functional verification by using FPGAs and a special compiler.      36.1 A General Probabilistic Framework for Worst Case Timing Analysis    Speaker(s): Michael Orshansky - Univ. of California, Berkeley, CA    Author(s): Michael Orshansky - Univ. of California, Berkeley, CA Kurt Keutzer - Univ. of California, Berkeley, CA      36.2 False Timing Path Identification using ATPG Technique and Delay-Based Information    Speaker(s): Jing Zeng - Motorola, Austin, TX    Author(s): Jing Zeng - Motorola, Austin, TX Magdy Abadir - Motorola, Austin, TX Jacob Abraham - Univ. of Texas, Austin, TX      36.3 False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation    Speaker(s): Jing Jia Liou - Univ. of California, Santa Barbara, CA    Author(s): Jing Jia Liou - Univ. of California, Santa Barbara, CA Angela Krstic - Univ. of California, Santa Barbara, CA Li C Wang - Univ. of California, Santa Barbara, CA Kwang Ting (Tim) Cheng - Univ. of California, Santa Barbara, CA      36.4 A Fast, Inexpensive and Scalable Hardware Acceleration Technique for Functional Simulation    Speaker(s): Srihari Cadambi - NEC, Princeton, NJ    Author(s): Srihari Cadambi - NEC, Princeton, NJ Chandra S. Mulpuri - NEC/Univ. of Washington, Princeton , NJ Pranav N. Ashar - NEC, Princeton, NJ